1. Field of the Inventive Concept
The inventive concept relates to semiconductor devices, methods related to semiconductor devices, and printed circuit boards incorporating semiconductor devices. More particularly, the inventive concept relates to semiconductor devices including an impedance circuit and an AC component interrupter, methods related to such semiconductor devices, and printed circuit boards incorporating an impedance circuit along with a semiconductor device.
2. Description of the Related Art
Semiconductor devices are used in high-speed and high-performance systems. Thus, a semiconductor device used in such a system needs a greater operating speed and a greater number of signal input and/or output terminals. In a semiconductor device, noise generated and/or induced over a power voltage or a ground voltage may be modeled as being proportional to the relationship (N×dI/dt), where “dI/dt” is a signal variation speed and “N” is a number of varying signals. This so-called “power voltage noise” may alter the perceived frequency of data/control signals or cause circuit malfunctions. Power voltage noise is proportional to the impedance of a terminal connecting element(s) internal to a semiconductor device and external element(s). Thus, power voltage noise may be generally reduced by reducing the apparent impedance of a connection terminal. One approach to reducing the impedance of any one connection terminal reduction suggests increasing the number of connection terminals provided by the semiconductor device.
FIG. 1 is a schematic diagram illustrating a conventional semiconductor device. The semiconductor device of FIG. 1 includes a chip 1 and a package 2.
Referring to FIG. 1, terminals 10-1 are power voltage terminals of chip 1, terminals 10-2 are ground voltage terminals of chip 1, terminals 20-1 are power voltage terminals of package 2, and terminals 20-2 are ground voltage terminals of package 2. Each terminal referred to herein may be a pad. In addition, VCCL is a power voltage line of chip 1, and GNDL is a ground voltage line of chip 1. When package 2 is a ball grid array (BGA) package, terminals 20-1 and 20-2 are balls, and when package 2 is a thin small outline package (TSOP), terminals 20-1 and 20-2 are pins. The power voltage line VCCL connects power voltage terminals 10-1 inside chip 1, and ground voltage line GNDL connects ground voltage terminals 10-2 inside chip 1.
FIG. 2 is an equivalent circuit diagram illustrating the semiconductor device of FIG. 1. In FIG. 2, “Rpkg” and “Lpkg” respectively represent a package resistance and a package inductance present in series between power voltage terminal 20-1 of package 2 and power voltage terminal 10-1 of chip 1. In addition, “Cdie” indicates a static capacitance present between power voltage line VCCL and ground voltage line GNDL, “I” indicates an electrical current that flows from power voltage line VCCL in chip 1 to ground voltage line GNDL, and “Vn” indicates power voltage noise.
A parallel resonant impedance Zp of the circuit illustrated in FIG. 2 is defined by Equation 1:
  ZP  =            Vn      I        =                  1                              j            ⁢                                                  ⁢            ω            ⁢                                                  ⁢            Cd            ⁢                                                  ⁢            i            ⁢                                                  ⁢            e                    +                      1                          Rpkg              +                              j                ⁢                                                                  ⁢                ω                ⁢                                                                  ⁢                Lpkg                                                        .      
A resonant frequency obtained using Equation 1 is
      1          2      ⁢      π      ⁢                        Cd          ⁢                                          ⁢          i          ⁢                                          ⁢          eLpkg                      .Power voltage noise Vn increases as electrical current I increases, and power voltage noise Vn has a maximum level at the resonant frequency. The resonant frequency is inversely proportional to inductance Lpkg, so when inductance Lpkg decreases, power voltage noise Vn decreases as well.
Accordingly, as one or more of the signal variation speed and the number of varying signals increases, electrical current I increases. Thus, power voltage noise Vn induced by the power voltage or the ground voltage also increases. In addition, when inductance Lpkg of package 2 increases, power voltage noise Vn increases.
However, because it is difficult to reduce the number of varying signals, power voltage noise Vn is reduced by increasing the number of power voltage terminals 20-1 and ground voltage terminals 20-2, which reduces the impedance of the terminals and thereby reduces inductance Lpkg of package 2.
However, while it is possible to increase the number of power voltage terminals 20-1 and ground voltage terminals 20-2 to reduce inductance Lpkg of package 2, increasing the number of power voltage terminals 20-1 and ground voltage terminals 20-2 has the disadvantage of increasing the size of package 2. That is, there is a limit to the amount that power voltage noise can be reduced by increasing the number of power voltage terminals 20-1 and ground voltage terminals 20-2. In addition, even though inductance Lpkg of package 2 can be reduced by increasing the number of terminals 20-1 and 20-2, increasing the number of terminals 20-1 and 20-2 shifts the resonant frequency to a frequency that is greater than an operable frequency of the semiconductor device and does not necessarily reduce the impedance at the resonant frequency. Thus, in the semiconductor device of FIG. 1, the power voltage noise which occurs at the resonant frequency may not be reduced.
FIG. 3 is a schematic diagram illustrating a conventional semiconductor device having a configuration intended to reduce power voltage noise. The semiconductor device of FIG. 3 is substantially the same as the semiconductor device of FIG. 1 except that the semiconductor device of FIG. 3 includes an impedance circuit 3 disposed between a power voltage terminal 20-1′ of power voltage terminals 20-1 of package 2 and ground voltage GND.
Referring to FIG. 3, impedance circuit 3 is disposed outside of package 2; however, impedance circuit 3 may be disposed inside package 2 and may be disposed inside chip 1. When impedance circuit 3 is disposed outside of package 2, impedance circuit 3 may be mounted on package 2.
FIG. 4 is an equivalent circuit diagram illustrating the semiconductor device illustrated in FIG. 3. In FIGS. 2 and 4, like reference symbols indicate like elements or values. In FIG. 4, “Rpkg1” and “Lpkg1” respectively denote a first package resistance and a first package inductance present in series between a power voltage terminal 20-1 of package 2 and a power voltage terminal 10-1 of chip 1. In addition, “Rpkg2” and “Lpkg2” respectively denote a second package resistance and a second package inductance present in series between power voltage terminal 20-1′ of package 2 and power voltage terminal 10-1 of chip 1.
In FIGS. 3 and 4, impedance circuit 3 may include a capacitor; a capacitor and a resistor connected to one another in series; or a capacitor, an inductor, and a resistor connected to one another in series. In other words, compared to the semiconductor device of FIG. 1, the semiconductor device of FIG. 3 additionally includes a serial resonant circuit between a power voltage terminal 20-1′ of power voltage terminals 20-1 and ground voltage terminal 20-2.
A parallel resonant impedance Zp of the circuit illustrated in FIG. 4 is defined by Equation 1 by replacing Rpkg, Lpkg into Rpkg1, Lpkg1, respectively, and a serial resonant impedance Zs of that circuit is defined by Equation 2:
  Zs  =            Vn      I        =          Rt      +                        j          ⁡                      (                                          ω                ⁢                                                                  ⁢                Lt                            -                              1                                  ω                  ⁢                                                                          ⁢                  Ct                                                      )                          .            
It is assumed in Equation 2 that impedance circuit 3 includes a capacitor, an inductor, and a resistor, wherein, in Equation 2, the capacitance of the capacitor, the inductance of the inductor, and the resistance of the resistor are represented by C, L, and R, respectively. Also in Equation 2, Rt denotes Rpkg2+R, Ct denotes
            C      ×      C      ⁢                          ⁢      d      ⁢                          ⁢      i      ⁢                          ⁢      e              C      +              C        ⁢                                  ⁢        d        ⁢                                  ⁢        i        ⁢                                  ⁢        e              ,and Lt denotes Lpkg2+L. A serial resonant frequency obtained by Equation 2 is
      1          2      ⁢      π      ⁢              CtLt              .Power voltage noise Vn increases as electrical current I increases, and power voltage noise Vn has a minimum level at the serial resonant frequency. Also, because the serial resonant frequency is inversely proportional to inductance Lt, power voltage noise Vn decreases as inductance Lt decreases.
Thus, the semiconductor device of FIG. 3 reduces power voltage noise Vn by making the resonant frequency of the serial resonant circuit and the resonant frequency of the parallel resonant circuit the same and offsetting a maximum value of power voltage noise Vn obtained by resonance of the parallel resonant circuit with a minimum value of power voltage noise Vn obtained by resonance of the serial resonant circuit. That is, the semiconductor device of FIG. 3 can reduce power voltage noise Vn by reducing the impedance at the resonant frequency.
Alternatively, though it is not shown, impedance circuit 3 may be disposed between a terminal 20-2′ of ground voltage terminals 20-2 and power voltage Vcc. In another alternative, an impedance circuit may be disposed between a terminal 20-1′ of power voltage terminals 20-1 of package 2 and ground voltage GND and another impedance circuit may be disposed between a terminal 20-2′ of ground voltage terminals 20-2 and power voltage Vcc.
Semiconductor devices analogous to the one illustrated in FIG. 3 are disclosed, for example, in U.S. Pat. No. 5,926,061.
Although the semiconductor device of FIG. 3 can be arranged such that it can reduce the AC component power voltage noise and such that impedance circuit 3 can reduce the impedance at the resonant frequency, the semiconductor device of FIG. 3 has the disadvantage of having a relatively large number of terminals receiving the power voltage or the ground voltage. Thus, the semiconductor device of FIG. 3 will suffer from a relatively large drop in the power voltage and/or ground voltage, so DC component power voltage noise will increase.
FIG. 5 is a schematic diagram illustrating a conventional printed circuit board (PCB). The PCB of FIG. 5 includes a substrate 30 having a plurality of layers, a semiconductor device 32, and decoupling capacitors 34-1 to 34-4. Substrate 30 includes signal line layers 30-1 and 30-4, a power voltage layer 30-2, and a ground voltage layer 30-3. In FIG. 5, the dots (“•”) each represent a connection to power voltage layer 30-2, and the “×”s each represent a connection to ground voltage layer 30-3.
FIG. 6 is an equivalent circuit illustrating the PCB of FIG. 5. In FIG. 6, “Cp” denotes a capacitance that exists in the PCB; Lt denotes an inductance between power voltage terminal 40-1 of substrate 30 and power voltage layer 30-2 of substrate 30; “Cd”, “Ld”, and “Rd” represent a capacitance, an inductance, and a resistance, respectively, of decoupling capacitors 34-1 to 34-4, which are represented by element 34 in FIG. 6; and “Vpn” represents the power voltage noise between power voltage line PVCCL and ground voltage line PGNDL of substrate 30. “Rpkg”, “Lpkg”, “Cdie”, and “I” represent the same values in FIG. 6 as in FIG. 2.
A parallel resonant impedance Za of the circuit of FIG. 6 is defined by Equation 3:
  Za  =            Vpn      I        =                  1                              j            ⁢                                                  ⁢            ω            ⁢                                                  ⁢            Cp                    +                      1                          Rd              +                              j                ⁡                                  (                                                            ω                      ⁢                                                                                          ⁢                      Ld                                        -                                          1                                              ω                        ⁢                                                                                                  ⁢                        Cd                                                                              )                                                                        +              j        ⁢                                  ⁢        ω        ⁢                                  ⁢        L        ⁢                                  ⁢        1.            
A resonant frequency obtained through Equation 3 is
      1          2      ⁢      π      ⁢              CdLd              .Power voltage noise Vpn increases as electrical current I increases, and power voltage noise Vpn has a maximum level at the resonant frequency. Also, since the resonant frequency is inversely proportional to inductance Ld, power voltage noise Vpn decreases as inductance Ld decreases.
Thus, in order to reduce the power voltage noise induced in the conventional PCB, the decoupling capacitors are added to thereby reduce inductance Ld. When “Ci”, “Li”, and “Ri” respectively represent a capacitance, an inductance, and a resistance of each of the decoupling capacitors, and N decoupling capacitors having the same capacitance, inductance, and resistance are connected to one another in parallel, the total capacitance, inductance, and resistance of the N decoupling capacitors are N×Ci, Li/N, and Ri/N, respectively. However, while power voltage noise can be reduced by reducing the inductance by adding decoupling capacitors to the PCB, adding the decoupling capacitors shifts the resonant frequency of the PCB to a frequency that is greater than an operable frequency of the semiconductor device mounted on the PCB, so the power voltage noise at the resonant frequency of the PCB of FIG. 5 cannot be reduced.